Renesas Electronics has developed three system-on-chip (SoC) technologies for automotive multi-domain electronic control units (ECUs), targeting the requirements of software-defined vehicle (SDV) architectures. The technologies, presented at the International Solid-State Circuits Conference (ISSCC) 2026 in San Francisco, address functional safety, AI processing quality, and power efficiency in next-generation automotive SoCs.
The first technology introduces a chiplet architecture supporting ASIL D functional safety. By combining the standard UCIe die-to-die interface with a proprietary RegionID mechanism, the design prevents hardware resource interference across simultaneous applications, achieving freedom from interference (FFI). Testing confirmed a transmission speed of 51.2 GB/s across the UCIe interface, approaching intra-SoC transfer speed limits.
The second development covers a 3nm SoC design that improves neural processing unit (NPU) performance while maintaining automotive-grade quality. As NPUs have grown around 1.5 times larger than previous generations, Renesas redesigned the clock architecture, introducing mini clock pulse generators (mCPGs) at the sub-module level to reduce latency and meet zero-defect timing requirements.
The third technology is an advanced power gating system using over 90 power domains, enabling precise control from milliwatts to tens of watts. Split power switches reduce IR drops by roughly 13% compared with conventional designs, while loopback monitoring and a digital voltage meter improve aging tolerance by 1.4 mV and support ASIL D compliance.
All three technologies are incorporated in Renesas’ R-Car X5H SoC for automotive multi-domain ECUs.
Source: Renesas
